FIFO memory is used to allow different data rates by controlling input and output rates

摘要

The first in first out, FIFO, memory (1) has data written at one rate and read at another dependent on a clock rate (CLK). Coupled to the FIFO memory is a memory control stage (2) that receives input from a pair of watchdog stages (3,4) that monitor input and output such that the clock signal can be controlled.