| 摘要 |
PURPOSE: A semiconductor integrated circuit device and layout thereof are provided to replace respectively an internal gate array, RAM macro cells or logic macro cells as a unit for feeding a clock signal from a plurality of final-stage distributing circuits, which are arranged so as to feed the clock signal at equal distances identically with first to third distributing circuits and succeeding distributing circuits, and to form the distributing circuits into ones synchronized with another without a difference in a clock signal delay. CONSTITUTION: A rectangular base chip(100) is formed on a main surface thereof with logic circuit blocks(10,8) composed of gate arrays and with memory blocks(7,9) including three pairs of memory portions(1). Each of the logic circuit blocks(10,8) is composed of an array of a plurality of basic cells(20). The logic circuit block(10) is divided into a plurality of logic circuit rows LB1 through LB6 by a plurality of stripe-like I/O (Input/Output) rows(15-19) while the logic circuit block(8) is divided into a plurality of logic circuit rows(LB7,LB8) by a stripe-like I/O row(13). Further, each of the logic circuit rows(LB1,LB8) is divided into a plurality of logic circuit cell units LCUs by reference voltage generating circuits RGs that run vertically relative to the I/O rows. In the device, the memory blocks(1-6) are arranged so that the blocks(1,4,2,5,3,6) are paired. The horizontally running three memory portions(1-3) constitute the memory block(7), while the horizontally running three memory blocks(4-6) constitute the memory block(9). Thus, the memory blocks(7,9) are arranged on the chip in a pair. A lateral size of each of the above-mentioned memory portions(1,6) is equivalent to a total size of four logic circuit cell units LCUs, maintaining integrity in layout with the logic circuit blocks(10,8) on the above-mentioned logic chip. Between the logic block(8) and the above-mentioned memory blocks(7,9), there are provided I/O portions(11,12) as interface circuits. Data processing and control for the memory portions are performed by the above-mentioned logic circuit block(8).
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