发明名称 METHOD FOR MANUFACTURING MOS TRANSISTOR USING SELF-ALIGNED SILICIDE TECHNOLOGY
摘要 PURPOSE: A fabrication method of an MOS transistor using a self-aligned silicide layer is provided to prevent dishing and junction spiking phenomena by using double metal silicide layers having different materials. CONSTITUTION: A stacked gate electrode(57a) and a silicidation resistant layer pattern are formed on an active region of a semiconductor substrate(51). An L-shaped screen oxide spacer(65a) and an insulating spacer(69) are sequentially formed at both sidewalls of a gate pattern. Source and drain regions(72) are formed by implanting heavily doped dopants into the semiconductor substrate(51) using the gate pattern and the spacers as a mask. A first metal silicide layer(73a) made of TiSi2 having excellent resistant against junction spiking is selectively formed on the source and drain regions(72). The gate electrode(57a) is exposed by removing the silicidation resistant layer pattern. A second metal silicide layer(75a) made of CoSi2 having low resistant dependency against the variation of line-width is selectively formed on the exposed gate electrode(57a).
申请公布号 KR20020083795(A) 申请公布日期 2002.11.04
申请号 KR20010023446 申请日期 2001.04.30
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, DO HYEONG;KWON, HYEONG SIN
分类号 H01L21/28;H01L21/336;H01L27/092;H01L29/423;H01L29/49;H01L29/78;(IPC1-7):H01L27/092 主分类号 H01L21/28
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