REFERENCE VOLTAGE GENERATOR IN FERROELECTRIC MEMORY DEVICE

摘要

PURPOSE: A reference voltage generator in a ferroelectric memory device is provided, which can perform a stable operation by increasing a uniformity of a reference voltage and also can reduce an area of the device by reducing the number of transistors to restore data of each reference cell. CONSTITUTION: N switching transistors(N is an even number)(N41-N4n) whose gates are connected to one reference word line is connected to a bit line. N ferroelectric capacitors(C41-C4n), whose one sides are connected to another sides of the above switching transistors and another sides are connected to a reference plate line(refpl), form one reference cell with one switching transistor. A PMOS transistor(P40) has a reference equalizing node(refeq) as a gate input, and restores data "1" to the odd-numbered capacitor by being connected to a storage node(lopre) of a reference cell which has a source connected to a power supply voltage port and a drain connected to an odd-numbered bit line. An NMOS transistor(N40) has a rest node as a gate input, and restores data "0" to the even-numbered capacitor by being connected to the storage node of the reference cell which has a source connected to a ground voltage port and a drain connected to an even-numbered bit line. And N/2 equalizing transistors(N51-N5n/2) have the reference equalizing node as gate inputs, and make an average of the data "1" and the data "0" by being connected to the storage nodes of the odd-numbered and the even-numbered reference cells.