| 摘要 |
PURPOSE: An encryption apparatus using a DES(Data Encryption Standard) algorithm is provided to reduce power consumption due to switching operations by decreasing a toggle speed and a toggle number. CONSTITUTION: The first to the fourth gate clocks(EN_CLK1 to EN_CLK4) have a period of 4T. The first multiplex portion(901) multiplexes a block b0. The first cypher function(950) encodes data of 32 bits according to the first auxiliary key. The second multiplex portion(902) multiplexes a block a0. The first exclusive logical OR operation portion(960) performs a logical operation for an output of the first cypher function(950) and an output of the second multiplex portion(902). The first left register(910) stores output data of the first exclusive logical OR operation portion(960) according to the first gate clock(EN_CLK1). The second cypher function(951) encodes the data of the first left register(910) according to the second auxiliary key. The second exclusive logical OR operation portion(961) performs a logical operation for an output of the second cypher function(951) and an output of the first multiplex portion(901). The first right register(920) stores an output of the second exclusive logical OR operation portion(961) according to the second gate clock(EN_CLK2). The third cypher function(952) encodes the data of the first right register(920) according to the third auxiliary key. The third exclusive logical OR operation portion(962) performs a logical operation for an output of the third cypher function(952) and an output of the first left register(910). The second left register(930) stores an output of the third exclusive logical OR operation portion(962) according to the third gate clock(EN_CLK3). The fourth cypher function(953) encodes the data of the second left register according to the fourth auxiliary key. The fourth exclusive logical OR operation portion(963) performs a logical operation for an output of the fourth cypher function(953) and an output of the first right register(920). The second right register(940) stores an output of the fourth exclusive logical OR operation portion(963) according to the fourth gate clock(EN_CLK4).
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