发明名称 UNSCRAMBLING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent an increase in a circuit scale by speedily performing processings, in an unscramble calculation processing. SOLUTION: By performing scramble calculations in a plurality of bits every time one piece of clock is inputted, by generating data of a plurality of bits in batch for performing the following scramble calculation from data for performing the preceding scramble calculation, by using a decoder circuit 5, and thus the time for processing the main data of all the data sectors by the unscramble calculations can be shortened, and a circuit composition also preventing increase in the circuit scale is realized.
申请公布号 JP2002319248(A) 申请公布日期 2002.10.31
申请号 JP20010125747 申请日期 2001.04.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MAEDA YASUTERU;TAKAYAMA TAKEYUKI
分类号 H04N5/92;G11B20/10;G11B20/14;(IPC1-7):G11B20/14 主分类号 H04N5/92
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