发明名称 COMMAND ISSUING DEVICE FOR FAST SERIAL INTERFACE
摘要 PROBLEM TO BE SOLVED: To reduce the load of command issue on a central processing unit(CPU) when an initiator function of SBP-2(serial bus protocol-2) is actualized. SOLUTION: This device is provided with a sequence control circuit 29 which is actuated by a CPU 10 to control a command issue sequence, a packet processing circuit 28 which constitutes an operation request block(ORB) to be issued in transmit packets and extract a status from a received packet, a buffer 30 which stores a command ORB registered by the CPU 10, a buffer 31 which stores a management ORB registered by the CPU 10, a buffer 32 which stores the received status for an issued management ORB and passes it to the CPU 10, and a buffer 33 which stores the received status for the issued command ORB and passes it to the CPU 10.
申请公布号 JP2002318777(A) 申请公布日期 2002.10.31
申请号 JP20010120745 申请日期 2001.04.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIMURA ISAMU;TAHIRA YOSHIHIRO
分类号 G06F13/12;G06F13/38;(IPC1-7):G06F13/12 主分类号 G06F13/12
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