| 摘要 |
Correction circuit 102 multiplies data subject to Rake combining from among data of a plurality of channels output from storage section 101 by correction coefficients and outputs the channel data to Rake section 103. Correction circuit 102 then multiplies the data of channels other than the channels subject to Rake combining by "0" and outputs the other channel data to Rake section 103. The value of the other channel data multiplied by "0" becomes "0" having no effect on the addition result of Rake combining. Rake section 103 applies a complex addition to the data output from correction circuit 102 and outputs the addition result to DSP 105.
|
