HIGH-VOLTAGE TRANSISTOR WITH EMBEDDED CONDUCTION LAYER

摘要

PROBLEM TO BE SOLVED: To provide a lateral high-voltage FET having a low on-state resistance and an embedded conduction layer. SOLUTION: A P-type embedded layer region is formed within an N-well, formed in a P-type substrate. The P-type embedded layer region is connected to a drain electrode by a first P-type drain diffusion region disposed in the N-well region the P-type embedded layer region is also connected to a second P-type drain diffusion region, which extends downward from the surface at the one end of the PMOS gate region, and a P-type source diffusion region, which is connected to the source electrode, defines the other end of the gate region.