发明名称 BIAS METHOD AND CIRCUIT FOR DISTORTION REDUCTION
摘要 <p>Bias circuit that generates the optimum bias voltage for a transistor at wich its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. Bias method by which currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity. A feedback circuit senses the DC signal and generates the bias voltage is applied to the main transistor resulting in cancellation of its selected nonlinearity.</p>
申请公布号 WO2002087072(A2) 申请公布日期 2002.10.31
申请号 US2002012190 申请日期 2002.04.17
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