| 摘要 |
<p>Testing an integrated circuit IC (2) with an embedded or integrated non-volatile memory (3), in particular a flash memory, an EPROM or EEPROM, is particularly difficult because mass production and low prices and minimal profit margins require that the testing, which usually requires expensive and large equipment, can be done in a minimum of time. Usually, the testing of an embedded memory (3) is a kind of bottleneck during manufacturing. The present invention describes a test structure and design and an associated test method which minimize this test time for an embedded memory. In essence, a few test devices (8, 9) integrated into the IC (2), use of the serial port provided on the IC, and an appropriate test design of a built-in self test whereby predetermined regular test patterns are written automatically into the embedded memory and an automated memory readout with automatically incremented addresses is compressed on the IC for a serial readout from it, allow a fast test of the embedded memory and thus circumnavigate the above-identified bottleneck.</p> |
