发明名称 Bus driving circuit and memory device having same
摘要 A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.
申请公布号 US2002159300(A1) 申请公布日期 2002.10.31
申请号 US20020176457 申请日期 2002.06.18
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 FUJIMOTO YUKIHIRO
分类号 G06F3/00;G11C7/10;H01L21/822;H01L27/04;(IPC1-7):G11C5/00 主分类号 G06F3/00
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