| 摘要 |
In electropolishing a metal layer on a semiconductor wafer, a dielectric layer (100) is formed on the semiconductor wafer (not shown). The dielectric layer (100) is formed with a recessed (102) area and a non-recessed (103) area. A plurality of dummy structures (200) are inactive areas configured to increase the planarity of a metal layer (106) subsequently formed on the dielectric layer (100). A metal layer (106) is then formed to fill the recessed (102) area and to cover the non-recessed (103) area and the plurality of dummy structures (200). The metal layer (106) is then electropolished to expose the non-recessed area (102). |
