POWER STANDBY CIRCUIT OF LOW−THRESHOLD MOS TRANSISTOR

摘要

A MOS semiconductor integrated circuit wherein the threshold values of MOSFETs (1, 2) are set low to realize the action of a low power source voltage VDD is provided with an nMOSFET (1) in a route of the drain current (Id) of the pMOSFET (2) to switch the route on/off, thereby controlling the impressing of a bias on the circuit (4). Thus, the gate−source voltage of the pMOSFET (2) is prevented from zeroing even when the bias is cut, so that a leak current from the pMOS (2) is blocked.