发明名称 SEMICONDUCTOR DEVICE, SYSTEM, AND METHOD
摘要 PURPOSE: To enable saving of a defective logical integrated circuit device or the like, incorporating a random access memory or the like after the product is shipped, to improve reliability of a computer system, and to realize redundancy of a memory, without having to alter the design of a memory block. CONSTITUTION: This device is provided with a redundant address decoder 11, in which memory blocks 100-104 are incorporated redundantly and a memory block being accessed can be changed, based on a result of a memory test of a block unit by a logical circuit 12; the saving after the product is shipped can be performed, by defining a decoding regulation from the result of the memory test, performing access avoiding access to a memory block including a defective element; and making it redundant is performed in a memory block level, and redundancy is realized without having to depend on the presence of a redundant circuit of a memory block itself.
申请公布号 KR20020082431(A) 申请公布日期 2002.10.31
申请号 KR20020021701 申请日期 2002.04.19
申请人 NEC ELECTRONICS CORPORATION 发明人 SHIONOYA SHINICHI
分类号 G01R31/28;G06F12/16;G11C29/00;G11C29/04;G11C29/12;G11C29/24;G11C29/26;(IPC1-7):G11C29/00 主分类号 G01R31/28
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