发明名称 Clock distribution circuit
摘要 <p>A user circuit unit is configured by a gate array, a PLL circuit is configured in a microprocessor macro unit, a clock frequency output from the PLL circuit in the microprocessor macro unit is directly distributed to a user circuit unit (CLK 3), and the clock frequency distributed to the user circuit unit is distributed to the microprocessor macro unit through a frequency divider configured by the user circuit unit.</p>
申请公布号 EP1253505(A2) 申请公布日期 2002.10.30
申请号 EP20020090157 申请日期 2002.04.25
申请人 NEC ELECTRONICS CORPORATION 发明人 AOKI, YOSHITAKA;IDA, NOBUO;HIKIBA, RUMI;NAKAJIMA, YOSHINOBU
分类号 G06F17/50;G06F1/10;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F1/04 主分类号 G06F17/50
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