| 摘要 |
PURPOSE: A capacitor fabrication method of an MML(Merged Memory Logic) device is provided to minimize area of capacitor and to increase a capacitance by forming a lower electrode using a plug processing. CONSTITUTION: An isolation layer(102) is formed at a field region of a semiconductor substrate(101) having a cell and a logic regions. A transistor having gate electrodes(104a,104b), and source and drain regions is then formed at an active region. After forming a first interlayer dielectric(106) on the resultant structure, a plurality of via holes are formed to expose the source and drain regions. A lower electrode(109a) is formed in the via hole of the logic region, and plugs(109b) are simultaneously formed in the via holes of the cell region. After forming an insulating layer(110) on the resultant structure, a contact hole is formed to expose the surface of the plug(109b). Then, an upper electrode(113a) is formed in the contact hole and a bit line(113b) is simultaneously formed on the logic region.
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