Self burn-in circuit for semiconductor memory

摘要

An improved self burn-in circuit for a semiconductor memory generates a control signal, an address, and a test data for a burn-in test operation when a certain self burn-in test condition is satisfied. The burn-in circuit includes a burn-in detector for generating a control signal, an address signal, and a test data for a burn-in test operation when a self burn-in test condition is achieved. A memory array performs a burn-in test operation when the test data is written into and/or read from a memory cell which is selected by the address signal in accordance with the control signal.