Digital phase-locked loop with phase optimal frequency estimation

摘要

A circuit is designed with a register circuit (70) arranged to store a control word. A voltage-controlled oscillator (73) is coupled to receive the control word (72) and produce a clock signal (76) having a current frequency corresponding to the control word. A phase detector circuit (53) is coupled to receive a reference signal (52) and the clock signal. The clock signal has one of a phase lead and a phase lag with respect to the reference signal. The phase detector circuit produces a phase signal (58) having a first state in response to the phase lead and having a second state in response to the phase lag. An estimate circuit (69) is coupled to the register circuit and the phase detector circuit. The estimate circuit produces a next control word (71) corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.