| 摘要 |
A method of manufacturing an embedded DRAM. A substrate has a memory cell region and a logic circuit region. A plurality of gate conductors are formed on the substrate in the memory cell region and the logic circuit region. A spacer is formed on a sidewall of each gate conductor. An epitaxy layer is formed selectively on the exposed area of the substrate surface to service as source/drain regions in the logic circuit region and a source region and a drain region in the memory cell region. A silicide layer is formed on the epitaxy layer. A conformal buffer layer is formed over the substrate, and then a dielectric layer is formed over the substrate to cover the gate conductors. A mask is formed on the dielectric layer to expose a DRAM cell bit line contact region and a logic device source/drain contact region at the same time. A first etching step is performed to remove the dielectric layer by using the barrier layer as an etching stop layer. Then, a second etching step is performed to remove the barrier layer for exposing the silicide layer. As a result, a DRAM cell bit line contact and a logic device source/drain contact in the memory cell region and in the logic circuit region are formed at the same time by using the first etching step and the second etching step. Finally, metal plugs are formed within the DRAM cell bit line contact and the logic device source/drain contact simultaneously.
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