发明名称 Phase-locked loop circuits for communication system
摘要 In a phase-locked loop circuit with a signal estimator such as MLSE or DDFSE for correctly detecting and correcting a phase deviation, the phase deviation is held within a predetermined value by amplitude limiting a phase deviation signal obtained from a received signal and a replica signal. Thus, the phase deviation signal is free from a large error irrespective of generation of an estimation error in the MLSE or DDFSE.
申请公布号 US6473470(B1) 申请公布日期 2002.10.29
申请号 US19990309830 申请日期 1999.05.11
申请人 NEC CORP. 发明人 MATUI HITOSI
分类号 H04L27/22;H04L7/00;H04L25/03;H04L27/00;(IPC1-7):H03D3/18;H03D3/24 主分类号 H04L27/22
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