发明名称 |
Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid |
摘要 |
A method for improving integrated circuit by using a patterned bump layout on a layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.
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申请公布号 |
US6473883(B1) |
申请公布日期 |
2002.10.29 |
申请号 |
US20010997437 |
申请日期 |
2001.11.29 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
BOBBA SUDHAKAR;THORP TYLER |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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