发明名称
摘要 PURPOSE: To provide a PMOS output circuit in which no current flows to a power supply even when a voltage is applied to an output terminal. CONSTITUTION: A back gate 2 of a PMOS transistor(TR) 1 of the output circuit is connected to a power supply 8 via a parasitic PNP TR 24 and NMOS TRs 35, 36 are conductive when an output terminal voltage is higher than the power supply voltage by a threshold voltage of a PMOS TR 81. Thus, the PMOS TR 1 is nonconductive and its drain and gate are short-circuited by the PMOS TR 11, then the reverse flow of a current from the output terminal to the power supply is prevented.
申请公布号 JP3338738(B2) 申请公布日期 2002.10.28
申请号 JP19950014191 申请日期 1995.01.31
申请人 发明人
分类号 H03K17/16;H03K17/567;H03K19/0175;H03K19/0944 主分类号 H03K17/16
代理机构 代理人
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