| 摘要 |
PURPOSE: A bus system is provided to supply a bus adapted to an embedded system and capable of reducing the number of interconnections and reducing a length of an interconnection. CONSTITUTION: Bus cells(204A-204N) connected to a plurality of data sources(202A-202N) are connected thereto in serial(block chain). The bus cells(204A-204N) form a block chain. In the case that a corresponding data source(202A-202N) is selected, the bus cells(204A-204N) constitute a path for making data being output from the data source(202A-202N) be loaded to a bus. The bus cells(204A-204N) have a bit connection circuit(206A0-206Am) with respect to each bit, thus one bus cell(204A-204N) has the 'M' number of bit connection circuits corresponded to the number of data bits. An output of each bit connection circuit included in a predetermined bus cell is supplied as an input of a bit connection circuit of an identical bit position included in a bus cell of the next end. In the case that short delay time is required in the data source(202A-202N), when the data source(202A-202N) is connected to the bus cell(204A-204N), it is desirable that the data source(202A-202N) is connected to a bus cell which is arranged adjacent to a data sink(208).
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