| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem of a prior art optimization method where a wiring interval is not taken into account at the time of minimizing a wiring delay that sufficient optimization is not ensured. SOLUTION: At first, the enlargement and contraction of the wiring width and wiring interval are defined virtually for an original wiring net at an RC network listing step 1 and all RC networks are listed based on the definition. At an altered RC network listing step 2, the insertion of a buffer and enhancement of the driving capacity of a drive side transistor (enlargement of transistor size) are effected for all RC networks determined previously while taking account of the inclination of an input waveform and an RC network of minimum path delay is determined. Finally, at a minimum delay RC network selecting step 3, an RC network of minimum delay is selected among groups of RC networks thus determined and a corresponding wiring layout is employed.
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