发明名称 CONTROL METHOD FOR DELAY AND CONSUMPTION POWER OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prepare a circuit having a high operation speed within a consumption power limit value when there is the consumption power limit value in a semiconductor integrated circuit. SOLUTION: The semiconductor integrated circuit is virtually constituted on a computer system, and delay in a path is calculated. Measures against delay are taken until consumption power exceeds the limit value according to the order of delay violation rates starting from the large violation rate. Delay violation rate is recalculated every time when operation speed of logic element is increased. The measures against delay are taken by changing internal resistance of the logic element, changing driving capability, and a threshold value of a transistor.
申请公布号 JP2002312415(A) 申请公布日期 2002.10.25
申请号 JP20010117614 申请日期 2001.04.17
申请人 HITACHI LTD 发明人 TAKIMOTO MISAO;SASAKI TETSUO;HIYAMA TORU
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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