| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor capable of shortening the latency of a loading/ storing command. SOLUTION: This processor is provided with a general purpose register 1, adder 2 for calculating virtual addresses, TLB 3 for converting a virtual address into a physical address, D-Cache 4, D-tag 5, data memory 6 whose capacity is smaller than that of the D-Cache 4 and whose speed is higher than that of the D-Cache 4, comparator 9 or comparing the output of the TLB 3 with the output of the D-tag 5 and comparator 10 for comparing the data read out from the D-Cache 4 with the data read out from the data memory 6. Since in the execution of a load command, the input of the succeeding command is executed using the data read out from the data memory 6 without waiting the hit detection results of the D-Cache D and the data memory 6, the latency of the loading command can be shortened, resulting in the improvement of the processor.
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