| 摘要 |
PROBLEM TO BE SOLVED: To solve problems of a conventional reception circuit (clock recovery circuit) that has had a large amplitude of a limit cycle signal and a feedback loop characteristic with large jitter dependence and signal level dependence (that is, difficulty in prediction of circuit characteristics). SOLUTION: The reception circuit including the clock recovery circuit is configured such that a phase comparator 5 compares phases of outputs received from a data detection determination circuit 1 for detecting and discriminating data of an input signal and a boundary detection determination circuit 2 for detecting and determination a boundary of the input signal, a clock signal generating circuit 4 receives an output of the phase comparator 5 to supply a 1st internal clock CLKd to the data detection determination circuit 1 and also to supply a 2nd internal clock CLKb to the boundary detection determination circuit 2, and a boundary skew generating circuit 3 controls the skew of the 2nd internal clock so as to change a detection timing of the boundary by the boundary detection determination circuit 2. |
