发明名称 LAYOUT METHOD FOR ELECTRONIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a layout method for an electronic circuit capable of guaranteeing signal reliability when designing circuit wiring layout. SOLUTION: A net list of the electronic circuit to be designed is inputted, and a layout plan is set (step S1). A structure of arranged wiring, electric characteristics of an electronic part connected with the structure (step S2), and normal operation conditions of a signal in a receiver for wiring are inputted (step S3). The maximum wiring length is calculated from these input data (step S4) and is compared with wiring length in the layout plan (step S5), and rearrangement of layout is performed until the wiring length in layout becomes below the maximum wiring length to obtain layout guaranteeing normal operation (step S6).
申请公布号 JP2002312413(A) 申请公布日期 2002.10.25
申请号 JP20010110251 申请日期 2001.04.09
申请人 NEC CORP 发明人 ABE HIROSHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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