| 摘要 |
PROBLEM TO BE SOLVED: To provide a device for designing the layout of a semiconductor integrated circuit in which enhancement in the performance of a logic circuit, high integration of placement and routing, high speed processing, and enhancement of productivity can be realized. SOLUTION: A layout section 11 performs the layout of a designed logic circuit. A delay analysis section 15 makes a decision whether a delay error is present or not from the layout results. If the delay error is present, a relay buffer insertion section 12 inserts a relay buffer so that the delay error is eliminated. When a block becoming an obstacle for routing is present at an insertion place, a relay buffer moving section 13 alters placement to the outside of the block. If no effect of a delay error improvement is attained, a relay buffer altering section 14 alters the number or the type of the relay buffer.
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