| 摘要 |
This invention implements a variable-length code pipeline decoding process as hardware by providing additional bit processing means, reducing the load on external control, and clarifying encoded data shift means. For this purpose, in order to determine a code length and additional bit length, two different decode processes are executed, the overall process is separated into three stages, i.e., a stage for shifting out a code word of encoded data, a decode processing stage, and a symbol determination & additional bit processing stage, and these stages are executed in a pipeline manner.
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