MOS-Halbleiteranordnung und Verfahren zu ihrer Herstellung

摘要

A MOS semiconductor device is disclosed which exhibits high switching operations including high turn-on and an excellent self-cooling capability. The device prevents damage to insulation films and electrodes thereof. An IGT includes a multi-layer structure having a p type emitter layer (1), an n type base layer (2), a p type base layer (3) and an n type emitter layer (4) are superimposed therein. A gate electrode (7) and an overlying gate oxide film (6) are disposed on a recessed surface (5a) of the multi-layer structure. A cathode electrode (8) is located only in and around a cathode surface (5) so that a most top surface of the gate electrode (7) is uncovered. Via an intervening cathode distortion snubbering plate (14), the cathode electrode (8) is in pressure contact with a cathode electrode body (15). The gate and the cathode electrodes (7) and (8) have a reduced capacitance therebetween. The cathode electrode body (15) serves to cool the cathode electrode (8). The gate electrode (7) and the gate oxide film (6) are protected from stress, and hence, will not be damaged by stress.