PROGRAMMABLE CONTROLLER

摘要

When an instruction code stored in a pipeline register (21d) is decoded by a decoding circuit (22a), it is judged, by decoding a device address, which device information on a RAM (11) or device information on a RAM (12) is used. If the device address designates the area of the RAM (12), the decoding circuit (22a) outputs a signal representing that the pipeline processing stop number is 0, unlike when the RAM (11) is designated. A pipeline register unit (21) does not outputs a signal representing that the pipeline stop signal is 1, so that the reading of the instruction code from the RAM (11) and the pipeline processing are not interrupted. As a result, a construction for executing a high-speed processing and a construction of a small size and a low price can be realized by a common hardware.