发明名称 |
Level sensitive latch |
摘要 |
A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter. The capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal O1={overscore (I1+Clk)}. A second inverter has as inputs capacitively coupled the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) to provide output (O2). A switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of: O2={overscore ((ClkxP)+O1)}.
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申请公布号 |
US2002153931(A1) |
申请公布日期 |
2002.10.24 |
申请号 |
US20010016153 |
申请日期 |
2001.12.10 |
申请人 |
CELINSKI PETER;ABBOTT DEREK;AL-SARAWI SAID |
发明人 |
CELINSKI PETER;ABBOTT DEREK;AL-SARAWI SAID |
分类号 |
H03K3/037;(IPC1-7):H03K3/037 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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