Clock synchronizing circuit and method of designing the same

摘要

The clock synchronizing circuit is provided with many sequential circuits which operate on the basis of same clock signal. The sequential circuits carries out sampling of input data and changing of output data at both rising and falling edge of the clock signal. The sequential circuits include input selector circuit which select either of two inputs in accordance with a test mode signal. Output of one sequential circuit is input into an input selector circuit of subsequent sequential circuit. Thus, a series of scan pass SP is formed.