发明名称 SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
摘要 <p>A system and method for testing a flash memory device (10) having uniform sectors (4, 5, 6) and smaller, &quot;boot&quot; sectors (0, 1, 2) includes determining uniform and boot test limits based on average erase (24) and APDE (28) time periods of the uniform (4, 5, 6) and boot sectors (0-2) respectively. In this way, the erase test results (24) for each sector type is compared (36) against test limits that are based only on that sector type, thereby avoiding excessive false rejects.</p>
申请公布号 WO2002084669(A1) 申请公布日期 2002.10.24
申请号 US2001045442 申请日期 2001.10.30
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