发明名称 |
SELF-ALIGNED METHOD FOR FORMING SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH VERTICAL CONTROL GATE SIDEWALLS, INSULATION SPACER AND MEMORY ARRAY MADE THEREBY |
摘要 |
PURPOSE: A self-aligned method for forming semiconductor memory array of floating gate memory cells is provided to align various components such as a source, a drain, a control gate and a floating gate by making each memory cell include a floating gate, the first terminal, the second terminal having a channel region between the floating gate and the first terminal and a control gate. CONSTITUTION: A plurality of spaced apart isolation region and active region are formed on a semiconductor substrate substantially parallel to one another in a column direction. Floating gates are formed in each of the active regions. Control gates are each formed with a substantially vertical face portion by covering a portion of a conductive layer with a protective layer, and by performing an anisotropic etch process to remove the exposed portion of the conductive layer. An insulation sidewall spacer is formed against the vertical face portion. The control gates have protruding portions that extend over the floating gates.
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申请公布号 |
KR20020080225(A) |
申请公布日期 |
2002.10.23 |
申请号 |
KR20010058202 |
申请日期 |
2001.09.20 |
申请人 |
SILICON STORAGE TECHNOLOGY, INC. |
发明人 |
CHERN GEENG CHUAN |
分类号 |
H01L21/28;H01L21/8247;H01L27/115;H01L29/423;H01L29/788;(IPC1-7):H01L27/115;H01L21/824 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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