发明名称 TESTING CIRCUIT OF INTEGRATED CIRCUIT DEVICE AND METHOD FOR TESTING
摘要 PROBLEM TO BE SOLVED: To enable non-defective/defective decision of each functional block to be easily executed by a little number of test/data inputting and a little number of output data bits in a short time in an integrated circuit device having a plurality of functional blocks. SOLUTION: The integrated circuit device 2 comprises a test data storage unit 3, a bus switching controller 4 for reading in parallel test data from the storage unit and imparting the read data to a plurality of functional blocks FB(1) to FB(n), each digit output data compressing unit 5 for processing to compress the outputs of the blocks at each digit, an overall digit output compressing unit 9 for further compressing the digit compressed outputs, an external output interface unit 10 for outputting the outputs of the overall digit output compressing unit to an external terminal, and a test command controller 8 receiving the test command from the tester to control the command. Thus, the tester side inputs a test command, compares the output data of the external output terminal with an expected value, and executes the non-defective/defective decision of the integrated circuit device.
申请公布号 JP2002311104(A) 申请公布日期 2002.10.23
申请号 JP20010121106 申请日期 2001.04.19
申请人 NEC MICROSYSTEMS LTD 发明人 AKASAKA MOTOO
分类号 G01R31/28;G06F11/22;H01L21/822;H01L27/04 主分类号 G01R31/28
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