发明名称 Semiconductor memory device, system, and method of controlling accessing to memory
摘要 <p>Test circuits 150 to 154, which determine whether memory blocks 110 to 114 including at least one redundant block are defective, are included in the memory blocks, respectively, A decoding rule generating circuit 13 so generates a decoding rule that a defective block can not be accessed, and outputs the generated decoding rule as a decoding-rule signal RUL. Under the decoding rule, the redundant address decoder 14 decodes the address signal ADDR, to permit access to the memory blocks except the defective block(s). &lt;IMAGE&gt;</p>
申请公布号 EP1251525(A1) 申请公布日期 2002.10.23
申请号 EP20020008850 申请日期 2002.04.19
申请人 NEC ELECTRONICS CORPORATION 发明人 SHIONOYA, SHINICHI
分类号 G11C29/04;G01R31/28;G06F12/16;G11C29/00;G11C29/12;G11C29/24;G11C29/26;(IPC1-7):G11C29/00 主分类号 G11C29/04
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