Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors

摘要

An apparatus and a method are provided to distribute interrupts from a system bus to Intel(R) Architecture (IA)-32 applications processors. The apparatus includes a bridge that couples a processor bus to the system bus. In addition, the bridge is coupled to an advanced programmable interrupt controller (APIC) by an APIC bus. The bridge monitors the system bus for interrupts and converts selected interrupt transactions into APIC messages. The bridge then sends the APIC messages to the APIC bus. Each of the applications processors is also coupled to one of many APIC buses. The applications processor that is the target of the interrupt transaction receives the APIC message and executes an interrupt handler routine. The apparatus and method also incorporate interrupt transaction buffering and throttling.