发明名称 Modified aggressive precharge DRAM controller
摘要 A modified aggressive precharge method and apparatus for controlling a DRAM or system of DRAMs. Groups of memory access commands are sent to a DRAM controller. A bank/row activate command indicator is associated with the beginning of each group, and a bank precharge command indicator is associated with the end of each group. Normally, the DRAM controller will close the bank/row corresponding to a group responsive to the bank precharge command indicator associated with the end of the group; but the DRAM controller may conditionally leave the bank/row open, as follows: The DRAM controller analyzes the command stream to determine whether first and second groups of memory access commands are directed to the same row and bank. If so, then the precharge command indicated at the end of the first group and the activate command indicated at the beginning of the second group are not executed. The effect is to leave the bank/row of the first group open so that the second group may access it without having to reopen it. Dead time associated with closing and re-opening the same bank/row is eliminated while the advantages of aggressive precharge are maintained.
申请公布号 US6470433(B1) 申请公布日期 2002.10.22
申请号 US20000562600 申请日期 2000.04.29
申请人 HEWLETT-PACKARD COMPANY 发明人 PROUTY BRYAN G;EMMOT DAREL N
分类号 G06F12/02;G06F13/16;G11C7/12;(IPC1-7):G06F12/00 主分类号 G06F12/02
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