发明名称 Structure and method for high speed sensing of memory arrays
摘要 A method for sensing the state of a memory cell includes both dynamic and static clamping of the bit line coupled to a memory cell. This dual clamping configuration/operation ensures a quick charge of the bit line while eliminating overcharging of the bit line. Thus, sensing the state of the memory cell is substantially independent of the size of the memory array. A sensing system for sensing the state of a memory cell can include a system bit line coupled to a terminal of the memory cell, a charge initiation device for activating a charge operation on the system bit line, and a control unit connected between the system bit line and the charge initiation device. The control unit includes a static clamp to charge the system bit line to a first predetermined voltage and a dynamic clamp to charge the system bit line to a second predetermined voltage.
申请公布号 US6469929(B1) 申请公布日期 2002.10.22
申请号 US20010935013 申请日期 2001.08.21
申请人 TOWER SEMICONDUCTOR LTD. 发明人 KUSHNARENKO ALEXANDER;DADASHEV OLEG
分类号 G11C7/06;G11C7/12;G11C16/24;G11C16/26;(IPC1-7):G11C16/04 主分类号 G11C7/06
代理机构 代理人
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