| 摘要 |
An interface circuit (10) for use in a read channel of mass data storage device and which is synchronous with a clock (CLK8) of the mass data storage device operates to receive data (12) coming into the circuit (10) controlled by an associated controller. The circuit (10) is easily configurable to process either a full word length at once, or by half-word portions. In the half-word mode, the data coming into the circuit is clocked into one of three data registers (18, 36, 38). When a flag (NZH, NZL) that indicates that data is starting is detected, the phase of the received data with respect to the clock is determined by comparing (50) the phase of the full word clock (CLK8) to the phase of a half-word clock (CLK4). If the clocks are in-phase, the first two registers (18,36) are selected to contain respective halves of the data word. If the clocks are out-of-phase, the second two registers (36,38) are selected to contain the respective halves of the data word. The word halves are directed by multiplexers to output registers (26,28) for delivery to the channel (14) of the mass data storage device.
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