| 摘要 |
A method of verifying semiconductor integrated circuit reliability allows reliability verification of a large-scale semiconductor integrated circuit without any omission. Step S12 is to obtain a sum total (Cio) of inner-cell input/output load capacities in a selected cell on the basis of input and output load capacities registered in a cell library database (1A), and step S13 is to obtain wiring capacitance (Cic) between cells. In step S14, the sum total (Cio) of inner-cell input/output load capacities and the wiring capacitance (Cic) between cells are added to obtain output-terminal load capacity (COUT). On the basis of the output-terminal load capacity (COUT), a failure rate (FOUT) of an intercellular interconnect line is obtained in step S15, and a failure rate (Fcell) of inner-cell interconnect lines is obtained in step S16 from an equation registered in the cell library database (1A). Then, those failure rates (Fcell, FOUT) are added to obtain a total failure rate (Ftotal) in step S17.
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