发明名称 |
Method of fabricating CMOS device with dual gate electrode |
摘要 |
A method of fabricating a dual gate electrode CMOS device having dual gate electrodes. An N+ poly gate is used for the nMOSFET and a metal gate is used for the pMOSFET. The N+ nMOSFET poly gate may be capped with a highly conductive metal to reduce its gate resistance. A sacrificial cap is used for the N+ poly gate to eliminate a mask level for the dual gate electrodes.
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申请公布号 |
US6468851(B1) |
申请公布日期 |
2002.10.22 |
申请号 |
US20020038886 |
申请日期 |
2002.01.02 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
ANG CHEW-HOE;LIM ENG-HUA;CHA RANDALL CHER LIANG;ZHENG JIA-ZHEN;QUEK ELGIN KIOK BOONE;ZHOU MEI-SHENG;YEN DANIEL LEE-WEI |
分类号 |
H01L21/8238;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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