发明名称 Method and apparatus for dividing a store operation into pre-fetch and store micro-operations
摘要 A method of performing a store operation in a computer processor is disclosed. The method issues a store operation that is divided into a pre-fetch micro-operation that loads a needed cache line into a cache memory, and the subsequent store micro-operation stores a data value into the needed cache line that was pre-fetched into the cache memory.
申请公布号 US6470444(B1) 申请公布日期 2002.10.22
申请号 US19990334361 申请日期 1999.06.16
申请人 INTEL CORPORATION 发明人 SHEAFFER GAD S.
分类号 G06F9/312;G06F9/318;G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/312
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