Method and device for providing symetrical monitoring of ESD testing an integrated circuit

摘要

A method and a device (4) for testing an integrated circuit (DUT) uses a stress signal and surface monitoring. A stress signal generator (5) is connected to the integrated circuit (DUT) to apply the stress signal (v(t)) to the integrated circuit. A failure is observed in real time by monitoring the surface (6) of the integrated circuit (DUT) during a monitoring time window (DELTAT) by an emission microscope (10) having a controllable shutter (15). The time window has a predetermined relation with respect to the duration of the stress signal.