发明名称
摘要 An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits for performing a series of tests on an integrated circuit. The pattern generator is programmed to supply a sequence of pattern data as input to the tester circuits for controlling their operations during each test of the series. The pattern generator may also be programmed to interrupt the host computer before or during any test whenever it is necessary for the host computer to carry out an activity. The host computer may be programmed to respond to an interrupt by writing parameter control data into the tester circuits to reconfigure their operating characteristics, by acquiring test results from the tester circuits, or by directly controlling tester circuit operations during a test. When necessary to provide sufficient time for the host computer to carry out its task, the pattern generator may be programmed to temporarily suspend supplying pattern data to the tester circuits after sending an interrupt.
申请公布号 JP2002535682(A) 申请公布日期 2002.10.22
申请号 JP20000596386 申请日期 2000.01.03
申请人 发明人
分类号 G01R31/3183;G01R31/319;G06F11/22;(IPC1-7):G01R31/318 主分类号 G01R31/3183
代理机构 代理人
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