Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester

摘要

A driver circuit applies a write data whose level is inverted for every write cycle to a selected memory cell in accordance with a write data held by a latch circuit when a writing operation in a test operation mode is designated in the test operation mode. A read driver circuit applies a comparison result of sequentially read data to a latch circuit in accordance with a read clock signal in the test operation mode. Data input and output buffers operate in synchronization with an external clock signal.