发明名称 WAFER LEVEL CHIP SCALE PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 <p>PURPOSE: A wafer level CSP(Chip Scale Package) and a method for manufacturing the same are provided to prevent a crack and a short between solder balls by using long and thin metal films having flexibility and elasticity. CONSTITUTION: A semiconductor chip(1) has an active surface formed a bonding pad(3). A passivation layer(10) is formed on the active surface to expose the bonding pad(3). An insulating layer(220) is formed on the passivation layer. A lower metal film(230) is partially formed on the insulating layer so as to connect with the bonding pad(3). A first metal film(250a) is formed on the lower metal. A plurality of second metal films(250b) having long and thin mushroom shape are formed on the first metal film(250a). An electroless plating film(270) is formed on the first and second metal films(250a,250b), and a solder ball(260) is bonded to the electroless plating film(270).</p>
申请公布号 KR20020079136(A) 申请公布日期 2002.10.19
申请号 KR20010019842 申请日期 2001.04.13
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JANG, DONG HYEON;KANG, SA YUN;KWON, YONG HWAN;LEE, JIN HYEOK
分类号 H01L23/48;(IPC1-7):H01L23/48 主分类号 H01L23/48
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